As a high voltage field effect transistor, there is for example one disclosed in Japanese Unexamined Patent Publication No. 2003-204062.
For example as shown in FIG. 16 in the above patent Document, a high voltage nMOS transistor has a low concentration region (referred to as n-offset drain region 12 in this patent Document) and a high concentration region (referred to as n+offset drain region 17 in this patent Document) as drain regions. A gate oxide film 14 is formed so as to cover a channel formation region and an end of the low concentration drain region 12. A field oxide film 13 is formed in a region within the low concentration drain region 12 in which neither of the high concentration drain region 17 and the gate oxide film 14 is formed. A gate electrode 15 is formed so as to cover the gate oxide film 14 and an end section of the field oxide film 13. That is to say, the drain side end section of the gate electrode 15 is arranged on the field oxide film 13, not on the gate oxide film 14.
The drain region has a dual structure including the high concentration region 17 and the low concentration region 12, in order to improve the breakdown voltage between the source and the drain. If the distance of the low concentration region 12 is greater, that is, the distance between the channel formation region and the high concentration region 17 is greater, the breakdown voltage between the source and the drain can be improved.
Moreover, the reason the drain side end section of the gate electrode 15 is arranged on the field oxide film 13 is because an electric field is likely to concentrate in the vicinity of the end section of the gate electrode 15. That is to say, by arranging the end section of the gate electrode 15 on the field oxide film 13, electric field concentration within the drain region can be reduced, and the breakdown voltage of the MOS transistor increased.
As described above, in order to increase the breakdown voltage of the MOS transistor, it is preferable to increase the distance of the low concentration region, that is, to increase the distance between the channel formation region and the high concentration region.
However, there is a disadvantage in that if the distance of the low concentration region becomes greater, the on-resistance increases and the driving capacity of the MOS transistor decreases.
In addition, there is also a disadvantage in that when the distance of the low concentration region is made greater, the element area increases and integration of an integrated circuit decreases.
Here, even when the distance of the low concentration region is made greater, if the channel width is accordingly increased, an increase in the on-resistance can be prevented or suppressed. However, if the channel width of the MOS transistor is increased, the element area further increases and the problem of integration decrease becomes more significant.